The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs.
For example, a spacer technique is used to form fins for fin-like field effect transistor (FinFET) devices in order to meet increased demand for circuit density in spite of limitations of photolithography exposure tools. In a typical spacer technique, a mandrel pattern is formed over a substrate by photolithography, and a spacer is formed on sidewalls of the mandrel pattern by deposition and etching processes. Then, the mandrel pattern is removed, leaving the spacer over the substrate. The spacer generally has a closed shape. Before etching the substrate, the typical spacer technique employs a cut process to cut out portions of the spacer, resulting in disjoined spacer patterns. The substrate is then etched with the disjoined spacer patterns as an etch mask thereby forming the fins. The portion of the substrate that corresponds to the cut-out portions of the spacer is removed during the etching process, wasting valuable resources.